EXTRA Exploiting eXascale Technology with Reconfigurable Architectures
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Publications

    2017
    1. A. Kulkarni, A. Werner, F. Fricke, D. Stroobandt and M. Huebner, "Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications" in 3rd International Workshop on Overlay Architectures for FPGAs (OLAF2017), Monterey, CA, USA, Feb. 22, 2017, 2017.
    2016
    1. A. Kulkarni and D. Stroobandt, "MiCAP-Pro: a high speed custom reconfiguration controller for Dynamic Circuit Specialization" in Design Automation for Embedded Systems, 2016, pp. 1--19.
    2. C. Kritikakis, G. Chrysos, A. Dollas and D. N. Pnevmatikatos, "An FPGA-based High-Throughput Stream Join Architecture" in 26th International Conference on Field-Programmable Logic and Applications (FPL), 2016.
    3. D. Stroobandt, A. L. Varbanescu, C. B. Ciobanu, M. Al Kadi, A. Brokalakis, G. Charitopoulos, T. Todman, X. Niu, D. Pnevmatikatos, A. Kulkarni, E. Vansteenkiste, W. Luk, M. D. Santambrogio, D. Sciuto, M. Huebner, T. Becker, G. Gaydadjiev, A. Nikitakis and A. J. Thom, "EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures" in Reconfigurable Communication-centric Systems-on-Chip, 2016, pp. 1--7.
    4. G. Natale, R. Cattaneo, G. Stramondo, P. Bressana, D. Sciuto and M. D. Santambrogio, "A Polyhedral Model-based Framework for Dataflow Implementation on FPGA devices of Iterative Stencil Loops" in International Conference On Computer Aided Design (ICCAD), 2016, pp. To Appear.
    5. A. Solazzo, E. Del Sozzo, I. De Rose, M. De Silvestri, G. C. Durelli and M. D. Santambrogio, "Hardware Design Automation of Convolutional Neural Networks" in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI‘16), July 2016, pp. To Appear.
    6. M. Rabozzi, G. C. Durelli, A. Miele, J. Lillis and M. D. Santambrogio, "Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, pp. 1-14.
    7. A. Kourfali and D. Stroobandt, "Efficient hardware debugging using parameterized FPGA reconfiguration" in 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016, pp. 277--282.
    8. A. Kulkarni, E. Vansteenkiste, D. Stroobandt, A. Brokalakis and A. Nikitakis, "A fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing applications" in 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016, pp. 265-270.
    9. E. Del Sozzo, A. Solazzo, A. Miele and M. D. Santambrogio, "On the Automation of High Level Synthesis of Convolutional Neural Networks" in 2016 IEEE International Parallel and Distributed Processing Symposium Workshop (IPDPSW) - RAW, May 2016, pp. To Appear.
    10. A. Kulkarni and D. Stroobandt, "How to Efficiently Reconfigure Tunable Lookup Tables for Dynamic Circuit Specialization" in International Journal of Reconfigurable Computing, 2016, pp. 12.
    11. R. Cattaneo, G. Natale, C. Sicignano, D. Sciuto and M. D. Santambrogio, "On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach" in ACM Trans. Archit. Code Optim., December 2015, pp. 53:1--53:26.
    2015
    1. A. Kulkarni, V. Kizheppatt and D. Stroobandt, "MiCAP: A custom Reconfiguration Controller for Dynamic Circuit Specialization" in ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on, Dec 2015, pp. 1-6.
    2. C. B. Ciobanu, A. L. Varbanescu, D. Pnevmatikatos, G. Charitopoulos, X. Niu, W. Luk, M. D. Santambrogio, D. Sciuto, M. A. Kadi, M. Huebner, T. Becker, G. Gaydadjiev, A. Brokalakis, A. Nikitakis, A. J. W. Thom, E. Vansteenkiste and D. Stroobandt, "EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing" in Proceedings of the 18th International Conference on Computational Science and Engineering (CSE 2015), October 2015, pp. 339-342.

    © 2015-2017 EXTRA

    The EXTRA project has received funding from the European Union Horizon 2020 Framework Programme (H2020-EU.1.2.2.) under grant agreement number 671653.