WP3 - Granularity Research and State-of-the-Art Architectures
RUB explained problems for the demonstator-applications high-level-synthesis. As a reminder, we said, that we tried to generate verilog code which is usable in VTR (Odin II front end parses only a subset of verilog) or blif-files which are usable in VPR. Also mentioned, we can generate usable blif files with quartus-hls if we do not use any additional blocks than LUTs and FlipFlops. But we also wanted to map applications on virtual FPGAs with additional hard blocks to examine effects of those hardware features. A couple of participants mentioned different tools for HLS. It would be great if we can name some of these tools here with a brief description and benefits.
State-of-The-Art Reconfigurable Architectures
During our last technical meeting we proposed to have a wiki to collect state-of-the-art reconfigurable architectures. The following set is already mentioned and explained in the upcoming deliverable D3.1. As discussed, project participants can add comments or other suggestions on mentioned as well as unmentioned architectures. We will consider your opinions, but because of an upcoming deadline, maybe not all of your mentioned architectures are considered in the deliverable.
Already described Architectures in D3.1
System on Chip for High Performance Applications
- Altera Stratix 10
- Xilinx Ultra Scale
HPC Systems with FPGA Accelerators
- Cray XD1
- Convey HC2
- Microsoft Catapult
- Maxeler MPX/MPC series
Coarse Grain Reconfigurable Devices
Devices with Reconfigurable Co-Processor
- PACT XPP
Devices with Reconfigurable Functional Unit
- Stretch S6000 Processor
- Partial Reconfigurable Multi Context FPGA
Devices with Reconfigurable Pipelines
- ALU array architecture
We looking forward for some feedback.